1. Field of the Invention
The present invention relates generally to differential signal output devices that output transmission data as differential signals and, in particular, to a differential signal output device used for a transmitter, etc., that performs high-speed serial transmission as represented by Serial-ATA and PCI Express.
2. Description of the Related Art
In recent years and continuing to the present, so-called high-speed serial transmission is known as a technique employed in many transmission interface standards to meet requirements for large-volume and high-speed data transmission between equipment, boards, and chips. In the high-speed serial transmission, a transmission signal obtained by superposing a clock (embedded clock) on a signal representing transmission data is transmitted from the transmitting side, and then the clock is extracted from the signal received on the receiving side to restore the transmission data based on the extracted clock.
Jitter in high-speed serial transmission is roughly divided into two types, namely random jitter and deterministic jitter. The random jitter is caused by thermal noise due to transistors, etc., and random noise such as 1/f noise. The deterministic jitter is caused by deterministic factors such as interference between the codes of transmission data.
Preemphasis is known as a technique for reducing the deterministic jitter caused by the frequency characteristic of a transmission line. As shown in FIG. 1, preemphasis is a technique in which the amplitude caused when a transmission signal varies is previously emphasized on the transmitting side so that errors in transmission data to be demodulated from the transmission signal on the receiving side are suppressed.
An example using the preemphasis technique includes a method for generating a transmission signal having a desired waveform to which preemphasis is applied in such a manner that a signal having an appropriate phase difference is input to two drivers using a timer controlled to perform the proper preemphasis on a transmission line and the outputs of the two drivers are added to each other via a resistance (see, for example, Patent Document 1).
Furthermore, another example includes a method for reducing the timing jitter inherent in the preemphasis in such a manner that the respective internal nodes of a buffer that outputs a transmission signal having an ordinary amplitude and a buffer that outputs an emphasis signal obtained by emphasizing the amplitude of the transmission signal are connected to each other via a capacitor (see, for example, Patent Document 2).
Furthermore, still another example includes a method for reducing the jitter caused by the frequency characteristic of a transmission line in such a manner that the function of adjusting impedance is selects one bit of the transmission data and one bit of inversion data an output unit on the transmitting side and the output impedance of a circuit on the transmitting side is caused to interface with the characteristic impedance of a transmission line, and provided with the function of preemphasis regardless of variations in elements constituting the circuit on the transmitting side (see, for example, Patent Document 3).
Patent Document 1: JP-A-2002-525977
Patent Document 2: JP-A-2006-109093
Patent Document 3: JP-A-2006-60751
FIG. 2 shows a case using an equivalent circuit as a model when power is supplied to a semiconductor integrated circuit constituting a general purpose differential signal output device. In FIG. 2, the power supplied from a power supply circuit 23 to the semiconductor integrated circuit 26 is stabilized on a PCB (Printed Circuit Board) by a stabilization capacitor 24. In addition, it is stabilized by a stabilization capacitor 25 even in a chip including the semiconductor integrated circuit 26.
Furthermore, a parasitic impedance exists in a line for supplying the power, and an impedance via a bonding wire for mounting the chip on the PCB is also added. Note that in the equivalent circuit shown in FIG. 2 these impedances are denoted as the impedances 27a and 27b. 
As the current supplied from the power supply circuit 23 varies, the power supply voltage of the semiconductor integrated circuit 26 is varied by the impedances 27a and 27b. Particularly, because the bonding wire has a large inductance component, the power supply in the chip may cause a ringing phenomenon responding to a rapid variation in the consumed current.
Moreover, recent high-speed serial transmissions have been made at wide band and have reached several GHz as a maximum frequency. Therefore, influence on the power supply voltage due to the variation in the consumed current due to a biased pattern of transmission data is not negligible.
FIG. 3 shows the configuration of the simplest output buffer used for a general purpose differential signal output device. When a “high level” signal is output from the output buffer shown in FIG. 3, an N-type MOS transistor 21 is turned off, while a P-type MOS transistor 22 is turned on. Therefore, the output voltage becomes equal to power supply voltage Vdd. On the other hand, when a “low level” signal is output from the output buffer, the N-type MOS transistor 21 is turned on, while the P-type MOS transistor 22 is turned off. Therefore, the output voltage becomes equal to ground voltage GND.
Here, when the power supply voltage varies, a potential difference between the power supply voltage Vdd and ground potential GND also varies. As a result, because the voltage at the rising edge or falling edge of the pulse of a transmission signal varies, pulse widths T1 and T2 of the transmission signal also vary. Such a variation in pulse width adversely affects the receiving side as jitter.
As described above, the methods described in Patent Documents 1 through 3 use a voltage difference between the power supply and ground as the reference for the amplitude of a transmission signal. Therefore, jitter caused by the variation in power supply voltage cannot be reduced.